The present invention relates to a data processing device and a method therefor.
Data processing devices have been recently manufactured at low cost due to the development of LSIs (large scale integrated circuits) and microcomputers. Along with this development, a system is herein proposed in which a low-cost microprocessor is connected to a data processing device to perform systematic operations. Using an LSI or microprocessor for arithmetic control or input/output control, unique processing is performed in accordance with specific software.
FIG. 1 shows an example of a data processing device which adopts the above system. A central processing unit 11 (to be referred to as a CPU 11 hereinafter) controls arithmetic operations in accordance with a program stored in a main memory unit 12 (to be referred to as an MMU 12 hereinafter) and supervises I/O devices (not shown) connected to a common bus 15.
Input/output processors 13 and 14 (to be referred to as IOPs 13 and 14 hereinafter) perform data transfer between the common bus 15 and the I/O devices. The CPU 11, the MMU 12, and the IOPs 13 and 14 are connected to the common bus 15.
In the data processing device shown in FIG. 1, the I/O devices occupy the common bus 15 to transfer address data and to exchange information with each other therethrough.
General programs including an operating system (to be referred to as an OS hereinafter) are stored in the MMU 12. The CPU 11 accesses the MMU 12 via the common bus 15 every time OS control is required. At this time, the CPU 11 occupies the common bus 15 and transfers data in predetermined units. Thereafter, the common bus 15 is open to other devices.
However, in the system described above, the CPU 11 frequently occupies the common bus 15 since the OS is enlarged in scale. This further increases the OS overhead, thus degrading the system performance.
A cache memory system is used to perform high speed processing so as to improve the performance of the CPU 11. The cache memory is a high speed memory for temporarily storing data transferred between the CPU 11 and the MMU 12. Although the storage capacity of the cache memory is small, data is smoothly transferred between the CPU 11 and the MMU 12 since a high-speed memory element is used.
The MMU 12 and the cache memory are each generally subdivided into blocks having a fixed length (32-byte to 64-byte length). Data stored in the MMU 12 is transferred to the cache memory in units of blocks. If the CPU 11 requires both a calculation of the number of instructions and also the next instruction, it first checks to see whether or not such data is stored in the cache memory. If the necessary data is stored in the cache memory, it is immediately read out therefrom. This data is stored as an address table in a memory which is a so-called directory in order to perform high-speed addressing. However, if the necessary data is not stored in the cache memory, a block including this data is read out from the MMU 12 and is transferred to the cache memory. At the same time, the block described above is used for processing by the CPU 11. One block generally holds a number of data which is larger than the data processed by one instruction. Further, in operation, necessary data is more likely to be included in the same block of the MMU 12. Therefore, according to the system described above, the processing speed of the computer is increased.
When the cache memory system is adopted, the performance of the CPU 11 is improved. However, hardware (the directory and its peripheral circuits) for controlling the CPU 11 is large in size. Further, the control system of the CPU 11 becomes complex. Therefore, the above system is not an optimal one since highly integrated memory elements are available at low cost.